1. Field of the Invention
The present invention relates to high-speed asynchronous digital signal level conversion circuits. More particularly, the present invention disclosed herein relates to a digital signal level conversion circuit operable at high speed by improving a conversion speed (or rate) of a conversion circuit for converting a low-voltage digital signal into a high-voltage digital signal between digital circuits having different power source voltages in an integrated circuit.
The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2005-S-073-02, Development of semiconductor circuit design based on the nano-scaled device] in Korea.
2. Discussion of Related Art
With an increase in power consumption in varieties of digital chips, reducing power consumption therein is regarded as an important subject toward which significant effort is being focused in order to improve power consumption rate.
In digital circuits with embedded CMOS devices, most power consumption is caused by the CMOS devices' switching operations. Dynamic power consumption P can be summarized as shown Equation 1, which is proportional to an operating frequency f and the square of a power source voltage V.P∝f×V2  [Equation 1]
Therefore, lowering a level of the power source voltage is effective in reducing power consumption in the digital circuits using CMOS devices. However, when the power source voltage is lowered in the digital circuit using CMOS devices, propagation delays lengthen to limit operation speeds thereof, as shown in Equation 2.
                    Propagation_Delay        =                              V            DD                                              (                                                V                  DD                                -                                  V                  TH                                            )                        2                                              [                  Equation          ⁢                                          ⁢          2                ]            
In Equation 2, VDD represents the power source voltage and VTH represents a threshold voltage of the CMOS device.
Considering such characteristics, the digital chips using CMOS devices are usually designed to use a lower power source voltage in circuit regions operable at low speed (or low frequency), and designed to use a higher power source voltage in circuit regions operable at high speed or requiring a high voltage, such as input/output buffers, which is helpful for reducing the overall rate of power consumption in the digital chips.
In the case of using two kinds of digital circuits having different power source voltages in a digital chip, a circuit for converting a high-level digital signal into a low-level digital signal and a circuit for converting a low-level digital signal into a high-level digital signal are required for the purpose of transferring signals between circuit blocks having different power source voltages.
With such digital signal level conversion circuits, the circuit converting a high-level digital signal into a low-level digital signal has a relatively simple structure without functional degradation, such as a decrease in operation speed. In contrast, as the circuit for converting a low-level digital signal into a high-level digital signal may cause static power dissipation and reduction in operation speed, there is a need for additional circuits to compensate for such problems.
FIG. 1 is a circuit diagram showing the simplest structure of a digital signal level conversion circuit for converting a low-level digital signal into a high-level digital signal, in which an inverter of a low power source voltage is serially coupled to an inverter of a high power source voltage.
However, the digital signal level conversion circuit 100 shown in FIG. 1 has a disadvantage in that static power may be inadvertently dissipated, as explained hereinafter.
First, when a signal of 0V is applied thereto as a low-level digital input signal DL, a voltage of a first node N1 goes to a level of a low power source voltage VDDL. In this case, when the relationship among the low power source voltage VDDL, a high power source voltage VDDH, and a threshold voltage VTH of a second PMOS transistor PM2 is satisfied as shown in Equation 3, the second PMOS transistor PM2 not being turned off operates in a linear or saturation region. Then, a static current continuously flows from the high power source voltage VDDH toward the ground GND, resulting in undesired static power consumption.(VDDH−VDDL)≧(VDDH−VTH, PM 2)  [Equation 3]
For the purpose of solving such a static power consumption problem, a cross-coupled level converter (CCLC) shown in FIG. 2 is a typical structure which is widely used for asynchronous digital signal level conversion.
FIG. 2 is a circuit diagram of a conventional digital signal level conversion circuit 200, and FIG. 3 is a timing diagram of the digital signal level conversion circuit 200 shown in FIG. 2.
The digital signal level conversion circuit 200 having the CCLC structure has problems in that a conversion speed of converting from a low level to a high level is slow at nodes N1 and N2 corresponding to drains of input transistors NM1 and NM2 when a low-level input signal DL changes to a low level from a high level, and the conversion speed become slower when an input low voltage digital signal level becomes lower relative to a high voltage digital signal level.
The reason for the slow conversion speed is as follows.
When an input signal DL of the signal level conversion circuit 200 shown in FIG. 2 is the low power source voltage VDDL (i.e., high level voltage of logic ‘1’), a first NMOS transistor NM1 and the second PMOS transistor PM2 are turned on while a second NMOS transistor NM2 and a first PMOS transistor PM1 are turned off. Thus, the first node N1 is set to 0V and the second node N2 is set to the high power source voltage VDDH. In this case, when the input signal DL goes to 0V (i.e., low level voltage of logic ‘0’) from the low power source voltage VDDL, the first NMOS transistor NM1 is turned off first to set the first node N1 to high impedance. At the same time, as an inverted input signal DLB turns to the level of the low power source voltage VDDL from 0V, the second NMOS transistor NM2 is turned on to change the second node N2 to 0V. Thereby, the first PMOS transistor PM1 is turned on to change a voltage of the first node N1 to the level of the high power source voltage VDDH.
Since the voltages of the nodes change through the aforementioned operation process, the voltage of the first node N1 goes to the high power source voltage VDDH from 0V after a time delay, as shown in FIG. 3, even if the input signal DL changes to 0V from the level of the low power source voltage VDDL.
In other words, when a gate of the first NMOS transistor NM1 is applied with the digital input signal DL that changes to 0V from the low power source voltage VDDL, it takes a long time to change a drain voltage of the first NMOS transistor NM1 to the high power source voltage VDDH from 0V, and the signal level conversion speed becomes slower as the low power source voltage VDDL becomes lower than the high power source voltage VDDH. This effect occurs in the same pattern at the second node N2 when the low-level input signal DL changes to the low power source voltage VDDL from 0V.
Such a conversion speed degradation problem in the digital signal level conversion circuit limits the overall operation speed that is necessary for the digital chip to operate at high speed. As a result, there are disadvantages in that the overall performance of the digital chip is worse, and that the technique for operating some circuits of the digital chip in the low power source voltage is inapplicable.